In recent years, lithium ion batteries have been used in portable apparatuses such as digital cameras. A lithium ion battery is easily damaged from overcharging or overdischarging, and is thus provided in a battery pack having a circuit to provide protection from overcharging and overdischarging.
A battery pack is provided with a protection IC (integrated circuit). A protection IC (integrated circuit) has an overcharge detection circuit, an overdischarge detection circuit, an overcurrent detection circuit, and the like embedded therein. Upon detection of overdischarge or overcurrent by the overdischarge detection circuit or the overcurrent detection circuit, an MOS transistor is turned off to stop discharging from the lithium ion battery. Further, upon detection of overcharge by the overcharge detection circuit, an MOS transistor is turned off to stop charging the lithium ion battery.
The above-noted overcharge detection circuit, overdischarge detection circuit, and overcurrent detection circuit measure respective detection time. When the detection time exceeds a predetermined time (i.e., delay time), overcharge detection, overdischarge detection, and overcurrent detection are accepted as true detection to turn off the MOS transistor, thereby avoiding malfunction. Namely, a predetermined length of time needs to pass before overcharge detection, overdischarge detection, and overcurrent detection are accepted as true detection.
The problem is that, since a predetermined length of time (i.e., delay time) is necessary for overcharge detection, overdischarge detection, and overcurrent detection, it takes a lengthy time to test protection ICs upon manufacturing thereof. In consideration of this, the above-noted predetermined length of time (i.e., delay time) is shortened or eliminated by setting a short time mode to the protection ICs at the time of testing.
Patent Document 1, for example, discloses switching the delay time of a comparator output between a normal-delay-time mode, a shortened-delay-time mode, and a no-delay-time mode based on a check as to which one of a high level (VDD), a middle level (VDD/2), and a low level (VSS) is applied as an input level to a test terminal.
In the related-art circuit, one of the three types of varied time modes, i.e., the normal-delay-time mode, the shortened-delay-time mode, and the no-delay-time mode, is selected by setting the input level of the test terminal to one of the high level (VDD), the middle level (VDD/2), and the low level (VSS).
Accordingly, the related-art circuit may need two inverters, one NOR gate, and three NAND gates as a check circuit for checking which one of the high level (VDD), the middle level (VDD/2), and the low level (VSS) is the input level of the test terminal. Further, a charge current to a condenser in an oscillator is changed (i.e., increased/decreased) in response to the result of a check made by the check circuit. With this arrangement, the oscillating frequency is adjusted (i.e., high/low) to switch the delay time.
This arrangement gives rise to problems in that the related-art circuit has a complex circuit configuration because of the need for such a check circuit, and in that a change in the charge current to the condenser may result in the detection accuracy of the overcharge detection circuit and the overdischarge detection circuit being lowered.